1. Field of the Invention
This invention relates to a process for fabricating interconnects, and more particularly, to a degradation-free, low-permissivity dielectrics patterning process for damascene. Conventional patterning process gives rise to degradation of the low-permissivity dielectric layer; the process of this invention lessens this degradation.
2. Description of Related Art
Conventionally, there are two methods for fabricating interconnects, wherein one method includes forming a metal layer electrically connected to a via, patterning the photoresist layer on the metal layer, performing an etching process on the metal layer, and depositing an inter-metal dielectric (IMD) layer to cover the patterned metal layer. The other conventional method includes a damascene process of forming a dielectric layer, patterning the dielectric layer, forming trenches by an etching process, and filling the trenches with metal.
In a damascene process, using low-permissivity dielectric as IMD can reduce the occurrence of parasitic capacitance between interconnects and the IMD layer, and it can further decrease the RC delay. The low-permissivity dielectric includes inorganic materials, such as HSQ and FSG, and organic materials, such as flare, SILK, and parylene.
FIGS. 1A to 1E are sectional views showing a conventional damascene process.
Referring to FIG. 1A, a dielectric layer 102 is formed on a planarized substrate 100, wherein the dielectric layer includes a via plug 103, such as tungsten, electrically connected to a conducting region (not shown) on the substrate 100. A low-permissivity IMD layer 104 is formed on the dielectric layer 102 and via plug 103. Then, a patterned photoresist layer 106 is formed on the IMD layer 104, wherein the pattern of the photoresist layer 106 exposes the area on the IMD layer 104 reserved for forming trenches.
Referring to FIG. 1B, an etching process, such as a reactive ion etching process (RIE), is performed on the IMD layer 104 by using photoresist layer 106 as a mask to from trenches 107 and expose the top of the via plug 103.
Referring to FIG. 1C, the photoresist layer 106 is stripped by a photoresist removal process, such as an oxygen plasma ashing process or a wet chemical removal process.
However, the photoresist removal process, such as an oxygen plasma ashing process or a wet chemical removal process, damages the side walls 105 of the IMD layer 104a, and sometimes even causes a jagged profile on the side walls 105. Furthermore, the low-permissivity dielectric material of the sidewalls 105 tends to absorb moisture after a photoresist removal process, such as an oxygen plasma ashing process or a wet chemical removal process. As a result, the material filled into the trench 107 in the follow-up metallization process doesn't attach to the side walls 105 well and this causes degradation.
Referring to FIG. 1D, a metal glue/barrier layer 108, conformal to the shape of the IMD layer 104a, is formed over the substrate 100 to increase the attachment between the metal layer formed in the follow-up process and other materials. Then, a metal layer 110 is deposited on the glue/barrier layer 108 and fills the trench 107.
Referring to FIG. 1E, the undesired metal layer 110 on the metal glue/barrier layer 108 is removed by a chemical mechanical polishing process (CMP) to expose the top of the IMD layer 104a. This forms a metal line 110a and a patterned metal layer. The metal line 110a is electrically connected to the via plug 103.
However, the liquid cleaner used in a follow-up post metal-CMP cleaning process sometimes reacts with the foregoing low-permissivity dielectric layer. Such a reaction increases the permissivity of the dielectric, and makes the surface 115 of the IMD layer 104a tend to absorb moisture, which further causes poor attachment between the IMD layer 104a and material formed on it.